/**
  ******************************************************************************
  * @file    gt32f030_spi.c
  * @author  GT Application Team
  * @version V1.0.0
  * @date    03-January-2025
  *       
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 Giantec Semicondutor Inc</center></h2>
  *
  *             http://www.giantec-semi.com/
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GT32F030_QSPI_H
#define __GT32F030_QSPI_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "gt32f030.h"
/** @defgroup SPI_function_configuration
  * @{
  */ 
typedef enum
{
  SPI_Phase_First = 0x00,
  SPI_Phase_Second = 0x01
}SPIPhase_TypeDef;
#define IS_SPI_PHASE(PHASE) (((PHASE) == SPI_Phase_First) || ((PHASE) == SPI_Phase_Second))

/** @defgroup SPI_function_configuration
  * @{
  */ 
  typedef enum
  {
    SPI_Mode = 0x00,
    SPI_Dual_Mode = 0x01,
    SPI_Quad_Mode = 0x02
  }SPIMode_TypeDef;
  #define IS_SPI_MODE(PHASE) (((PHASE) == SPI_Mode) || ((PHASE) == SPI_Dual_Mode) || ((PHASE) == SPI_Quad_Mode))

typedef enum
{
  SPI_Pole_Low  = 0x00,
  SPI_Pole_High = 0x01
}SPIPole_TypeDef;
#define IS_SPI_POLE(POLE) (((POLE) == SPI_Pole_Low) || ((POLE) == SPI_Pole_High))

typedef enum
{
  SPI_Terminal_Slaver = 0x00,
  SPI_Terminal_Master = 0x01
}SPITerminalType_TypeDef;
#define IS_SPI_TERMINAL(TERMINAL) (((TERMINAL) == SPI_Terminal_Slaver) || ((TERMINAL) == SPI_Terminal_Master))
/** 
  * @brief   SPI Init structure definition  
  */ 
  typedef struct
  {	
    SPIPhase_TypeDef        SPI_Phase; 
    SPIPole_TypeDef         SPI_Pole;  
    SPITerminalType_TypeDef SPI_Terminal;     	
    uint8_t    ClockDivide;
    uint8_t    ClockRate;
  }SPI_InitTypeDef;

/** @defgroup SPI_Exported_Constants
  * @{
  */ 

#define IS_SPI_ALL_PERIPH(QSPIx)  (((PRESCALE) == QSPI1)  || \
																		((PRESCALE) == QSPI2))
  /**
    * @}
    */ 


/** @defgroup SPI_data_size 
  * @{
  */
  #define SPI_DataSize_32b                ((uint8_t)0xF8)
  #define SPI_DataSize_24b                 ((uint8_t)0xB8)
  #define SPI_DataSize_16b                 ((uint8_t)0x78)
  #define SPI_DataSize_8b                  ((uint8_t)0x38)
  #define SPI_DataSize_4b                 ((uint8_t)0x18)
  #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \
                                     ((DATASIZE) == SPI_DataSize_24b) || \
                                      ((DATASIZE) == SPI_DataSize_16b) || \
                                      ((DATASIZE) == SPI_DataSize_8b) || \
                                      ((DATASIZE) == SPI_DataSize_4b))                                      
  /**
    * @}
    */ 

  /** @defgroup SPI_GET_IT 
  * @{
  */
  #define SPI_IT_RECV                  ((uint32_t)1<<18)
  #define SPI_IT_RECV_TIMEOUT                 ((uint32_t)1<<16)
  #define  IS_SPI_GET_IT(IT_POS) (((IT_POS) == SPI_IT_RECV)) || \
                                ((IT_POS) == SPI_IT_RECV_TIMEOUT)
    /**
    * @}
    */ 
      /** @defgroup Clears the SPIx Interrupt flag 
  * @{
  */
  #define SPI_IT_RECV_CLR                  ((uint32_t)1<<18)
  #define SPI_IT_RECV_TIMEOUT_CLR                 ((uint32_t)1<<16)
  #define  IS_SPI_CLR_IT(IT_POS) (((IT_POS) == SPI_IT_RECV_CLR)) || \
                                ((IT_POS) == SPI_IT_RECV_TIMEOUT_CLR)
    /**
    * @}
    */ 



#define SPI_SSNOutput_Low   ((uint8_t)0x00)
#define SPI_SSNOutput_High  ((uint8_t)0x01)
#define IS_SPI_SSNOUTPUT(SSN) (((SSN) == SPI_SSNOutput_Low) || ((SSN) == SPI_SSNOutput_High))
/**
  * @}
  */ 

/** @defgroup SPI_FirstBit_Selection
  * @{
  */

typedef enum {
  SPI_FirstBit_MSB = 0x00,
  SPI_FirstBit_LSB = 0x01,
} SPIFirstBit_TypeDef;

#define IS_SPI_FIRSTBIT(CFG) (((CFG) == SPI_FirstBit_MSB) || ((CFG) == SPI_FirstBit_LSB))

/**
  * @}
  */

/* Exported types ------------------------------------------------------------*/




/* Exported functions --------------------------------------------------------*/
  void SPI_DeInit(QSPI_TypeDef* QSPIx);
  void SPI_Init(QSPI_TypeDef* QSPIx, SPI_InitTypeDef* SPI_InitStruct);
  void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
  void SPI_RunCmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_RECV_IRQ_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_RECV_TIMEOUT_IRQ_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  ITStatus SPI_GetITStatus(QSPI_TypeDef* SPIx, uint32_t SPI_IT);
  void SPI_ClearFlag(QSPI_TypeDef* SPIx, uint32_t SPI_FLAG);
  void SPI_DataSizeConfig(QSPI_TypeDef* SPIx, uint8_t SPI_DataSize);
  void SPI_DMACmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_SendData(QSPI_TypeDef* SPIx, uint32_t Data);
  void SPI_SendCommand(QSPI_TypeDef* SPIx, uint8_t Command);
  uint32_t SPI_ReceiveData(QSPI_TypeDef* SPIx);
  void SPI_Read_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_Lock_CS_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_Halfduplex_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  FlagStatus  SPI_GetBusyStatus(QSPI_TypeDef* SPIx);
  void SPI_TransmitLength(QSPI_TypeDef* SPIx, uint32_t length);
  void SPI_QPIMode_Cmd(QSPI_TypeDef* SPIx, FunctionalState NewState);
  void SPI_Mode_Sel(QSPI_TypeDef* SPIx, SPIMode_TypeDef Mode);

void SPI_FirstBitConfig(QSPI_TypeDef* SPIx, SPIFirstBit_TypeDef FirstBit);
uint32_t SPI_ReceiveData32(QSPI_TypeDef* SPIx);
uint32_t SPI_GetReceiveFIFOLevel(QSPI_TypeDef* SPIx);
uint32_t SPI_GetTransmitFIFOLevel(QSPI_TypeDef* SPIx);

#ifdef __cplusplus
}
#endif

#endif /* __GT32F030_SPI_H */

/**
  * @}
  */ 

/**
  * @}
  */ 

/************************ (C) COPYRIGHT Giantec Semicondutor Inc *****END OF FILE****/
